EdgeDetect erroneous output on first sample

Tech Note: TN0910
Product: RPvdsEx
Version: All
Date Added: 2012-11-29


The EdgeDetect component outputs a one sample TTL pulse when the input changes states. At start up, the 'previous state' is initialized incorrectly which can cause the component to send a false trigger at start up under the following conditions:

  1. Edge=Falling and initial input is 0.

  2. Edge=Rising and initial input is 1.


The circuit below uses a Not and OneShot component to ensure the output during the first sample is 0. If you have multiple EdgeDetect components in your circuit, you can reduce your component count by using the EDEnab hop.