Skip to content

FO5 Tech Notes

Cycle Usage exceeds 100% on auxiliary processors during large data transfers

TN0205

Product: PO5, FO5
Version: All
Date Added: 2006-03-20

Issue

The RX devices utilize a multi-DSP architecture that relies upon the Main processor to control a shared bus. As a result, the auxiliary processors may be unable to access the shared bus and memory when transfer rates are high. When they can access the bus the load on the processor can cause cycle usage to exceed 100%, resulting in timing errors or other difficult to detect errors.

Workaround

Users must be aware of this limitation and make sure that the cycle usage on all processors never exceeds 100% during maximum transfer. Refer to the MultiProcessor Circuit Design section of the RPvdsEx Manual for more information.